Usr-es1 embedded Wiznet W5500 chip, the use of hardware logic gate circuit to achieve the TCP/IP protocol stack of the transmission layer and network layer (such as: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE and other protocols), and the integration of the data link layer, the physical layer, and 32K byte chip RAM as the data transceiver cache.So that the host computer chip, only to undertake the TCP/IP application layer control information processing task.Thus greatly saves the upper computer for data replication, protocol processing and interrupt processing and other aspects of the workload, improve the system utilization and reliability.
In the process of operation, users can approximately use W5500 as a peripheral RAM of MCU, which is very simple.The external interface of W5500 is a universal 80MHz high-speed SPI, which is used for the expansion of high-speed Ethernet schemes for different platforms.
Wiznet embedded W5500 chip,80MHz high-speed SPI interface.
Built-in hardware TCPIP protocol stack, users almost no need to master the complex network protocol knowledge.
Support up to 8 Socket connections.
Support TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE protocol.
Integrated data link layer, physical layer.
Support power off and wake up.
Support high-speed serial peripheral interface (SPI mode 0-3)